Kiwi DVK board has a DIP switch configuration to enable/disable PCIe connections to the CPU, as some of them share the same PCIe lanes as a result of a limited PCIe lanes to the CPU.

To better understand the table lets find out which code corresponds to its PCIe connection on the Kiwi DVK board

• A+E Slot 0 is M2_SLOT_0
• B+M Slot 0 is M2_B_KEY_SLOT_1
• A+E Slot 1 is M2_SLOT_1
• mPCIe_SLOT_0 is sharing lanes with B+M Slot 1 -
• B+M Slot 1 is M2_B_KEY_SLOT_0

Knowing this we can deduct from the table:

• Setting SEL_PCIE1 off → enables M2_SLOT_0, and disabled M2_B_KEY_SLOT_1. Setting it on - enables M2_B_KEY_SLOT_1 and disables M2_SLOT_0
• Setting SEL_PCIE0 off → enables mPCIe_SLOT_0 and disables M2_B_KEY_SLOT_0. Setting it on - enables M2_B_KEY_SLOT_0 and disables mPCIe_SLOT_0.
• M2_SLOT_1 is always enabled as it does not share any PCIe lanes.